----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:52:27 03/03/2012 
-- Design Name: 
-- Module Name:    Cyclone - Struct
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.all;

entity Cyclone is
	port ( 
		clki : in std_logic;
		clri : in std_logic
	);
end Cyclone;

architecture Struct of Cyclone is


component Processor is 
	 Port ( clk_i : in  STD_LOGIC;
			  clr_i : in STD_LOGIC;
           instr_ack_i : in  STD_LOGIC;
           instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           data_ack_i : in  STD_LOGIC;
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           int_req : in  STD_LOGIC;
           port_ack_i : in  STD_LOGIC;
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           instr_cyc_o : out  STD_LOGIC; --
           instr_stb_o : out  STD_LOGIC; --
           instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
           data_we_o : out  STD_LOGIC;
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           int_ack : out  STD_LOGIC;
           port_cyc_o : out  STD_LOGIC;
           port_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
end component Processor;

component dataMem is
	port (	
			clk_i : in STD_LOGIC;
			data_cyc_i : in STD_LOGIC;
			data_stb_i : in STD_LOGIC;
			data_we_i : in STD_LOGIC;
			data_ack_o : out std_logic;
			data_addr_i : in std_logic_vector(7 downto 0);
			data_word_i : in std_logic_vector(7 downto 0); 		
			data_word_o : out std_logic_vector(7 downto 0)
	);
end component dataMem;

component instructionsMem is
	port(
		clk_i : in STD_LOGIC;
		instr_cyc_i : in STD_LOGIC;		
		instr_stb_i : in STD_LOGIC;
		instr_ack_o : out STD_LOGIC;
		instr_addr_i : in STD_LOGIC_VECTOR (9 downto 0);		
		instr_word_o : out STD_LOGIC_VECTOR (17 downto 0)
	);
end component instructionsMem;


component io is
			
	port (	
			clk_i : in STD_LOGIC;
			port_cyc_i : in STD_LOGIC;
			port_stb_i : in STD_LOGIC;
			port_we_i : in STD_LOGIC;
			port_ack_o : out std_logic;
			port_addr_i : in std_logic_vector(7 downto 0);
			port_word_i : in std_logic_vector(7 downto 0); 		
			port_word_o : out std_logic_vector(7 downto 0);
			int_req_o: out std_logic;
			int_ack_i: in std_logic
	);
end component io;

 signal instr_ack_i :STD_LOGIC;
 signal instr_word_i :STD_LOGIC_VECTOR (17 downto 0);
 signal data_ack_i :STD_LOGIC;
 signal data_word_i :STD_LOGIC_VECTOR (7 downto 0);
 signal int_req :STD_LOGIC;
 signal port_ack_i :STD_LOGIC;
 signal port_word_i :STD_LOGIC_VECTOR (7 downto 0);
 signal instr_cyc_o :STD_LOGIC;
 signal instr_stb_o :STD_LOGIC;
 signal instr_addr_o :STD_LOGIC_VECTOR (9 downto 0);
 signal data_cyc_o :STD_LOGIC;
 signal data_stb_o :STD_LOGIC;
 signal data_we_o :STD_LOGIC;
 signal data_addr_o :STD_LOGIC_VECTOR (7 downto 0);
 signal data_word_o :STD_LOGIC_VECTOR (7 downto 0);
 signal int_ack :STD_LOGIC;
 signal port_cyc_o :STD_LOGIC;
 signal port_stb_o :STD_LOGIC;
 signal port_we_o :STD_LOGIC;
 signal port_addr_o :STD_LOGIC_VECTOR (7 downto 0);
 signal port_word_o :STD_LOGIC_VECTOR (7 downto 0);

begin

proc:Processor port map(
	clk_i =>clki,
	clr_i =>clri,
	instr_ack_i =>instr_ack_i,
	instr_word_i =>instr_word_i,
	data_ack_i =>data_ack_i,
	data_word_i =>data_word_i,
	int_req =>int_req,
	port_ack_i =>port_ack_i,
	port_word_i =>port_word_i,
	instr_cyc_o =>instr_cyc_o,
	instr_stb_o =>instr_stb_o,
	instr_addr_o =>instr_addr_o,
	data_cyc_o =>data_cyc_o,
	data_stb_o =>data_stb_o,
	data_we_o =>data_we_o,
	data_addr_o =>data_addr_o,
	data_word_o =>data_word_o,
	int_ack =>int_ack,
	port_cyc_o =>port_cyc_o,
	port_stb_o =>port_stb_o,
	port_we_o =>port_we_o,
	port_addr_o =>port_addr_o,
	port_word_o =>port_word_o
);


dmem:dataMem port map(
	clk_i=>clki,
	data_cyc_i => data_cyc_o,
	data_stb_i => data_stb_o,
	data_we_i => data_we_o,
	data_ack_o => data_ack_i,
	data_addr_i =>data_addr_o,
	data_word_i => data_word_o,
	data_word_o => data_word_i
);

imem:instructionsMem port map(
	clk_i => clki,
	instr_cyc_i => instr_cyc_o,
	instr_stb_i => instr_stb_o,
	instr_ack_o => instr_ack_i,
	instr_addr_i => instr_addr_o,
	instr_word_o => instr_word_i
);

ioMem:io port map(
	clk_i=>clki,
	port_cyc_i => port_cyc_o,
	port_stb_i => port_stb_o,
	port_we_i => port_we_o,
	port_ack_o => port_ack_i,
	port_addr_i =>port_addr_o,
	port_word_i => port_word_o,
	port_word_o => port_word_i,
	int_req_o => int_req,
	int_ack_i => int_ack
);

end Struct;

